1. Field of the Invention
The present invention relates to semiconductor circuits, shift register circuits, and display devices, and particularly, relates to a semiconductor circuit, a shift register circuit, and a display device which are formed on an insulating substrate. The present invention also relates to an electronic apparatus in which such a display device is incorporated.
2. Description of the Related Art
In general, a known semiconductor circuit, for example, a shift register circuit uses a single phase clock as a reference clock for an operation in order to reduce power consumption, and uses a latch circuit in order to improve a potential holding characteristic and in order to operate even in a case where a device having a poor transistor characteristic such as a low-temperature polysilicon is employed (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2002-175050 and 10-302494).
In not only a transistor using a low-temperature polysilicon but also a transistor using a silicon having a defect, a characteristic of the transistor statically or dynamically (transiently) changes (for example, refer to “Characterization of Switching Transient Behavior in Polycrystalline-Silicon Thin-Film Transistors,” Hiroyuki Ikeda, Japanese Journal of Applied Physics Vol. 43, No. 2, 2004, pp. 477-484).
FIG. 10 shows a configuration of a shift register circuit according to Japanese Unexamined Patent Application Publication No. 2002-175050. In FIG. 10, although only an n-th transfer stage (unit circuit) 101n and an (n+1)th transfer stage 101n+1 are shown for simplicity, other transfer stages have the same configurations. Detailed description of the configurations will be made by taking the n-th transfer stage 101n as an example.
In FIG. 10, a switch 103 is connected between a clock line 102 and the n-th transfer stage 101n. The switch 103 is controlled to be turned on and off using a clock selection control circuit, which will be described later, so as to selectively supply a single-phase horizontal transfer clock HCK transmitted from the clock line 102 to the n-th transfer stage 101n. 
The n-th transfer stage 101n includes a latch circuit 104 which latches the horizontal transfer clock HCK selectively supplied through the switch 103, a buffer circuit 105 which outputs a latch pulse supplied from the latch circuit 104, and a clock selection control circuit such as an OR circuit 106 which controls the switch 103 in accordance with a latch pulse Ain output from a (n−1)th transfer stage and a latch pulse Aout output from the n-th transfer stage 101n itself.
FIG. 11 shows a configuration of the latch circuit 104. As shown in FIG. 11, the latch circuit 104 includes a CMOS inverter 201 having a P-channel MOS transistor Qp201 and an N-channel MOS transistor Qn201, and a CMOS inverter 202 having a P-channel MOS transistor Qp202 and an N-channel MOS transistor Qn202. An input terminal (a common connection node of the gate of the transistor Qp201 and the gate of the transistor Qn201) of the CMOS inverter 201 is connected to an output terminal (a common connection node of the drain of the transistor Qp202 and the drain of the transistor Qn202) of the CMOS inverter 202. An input terminal (a common connection node of the gate of the transistor Qp202 and the gate of the transistor Qn202) of the CMOS inverter 202 is connected to an output terminal (a common connection node of the drain of the transistor Qp201 and the drain of the transistor Qn201) of the CMOS inverter 201.
Operation of the latch circuit 104 having the configuration described above will now be described with reference to FIG. 12 which shows a waveform timing chart illustrating a change of an input/output potential of the latch circuit 104. Note that a shift register circuit is a unique circuit characterized by outputting a signal which is in a low level state (hereinafter referred to as an “L-level” state) for a long period of time and which is in a high level state (hereinafter referred to as an “H-level” state) for a short period of time. The “L-level” and the “H-level” can be reversed in accordance with logic of the shift register circuit.
In a period A in which the switch 103 shown in FIG. 10 is in an off-state, since an input/output potential of the latch circuit 104, that is, a potential of the input terminal of the CMOS inverter 201 is in the L-level state (for example, a ground (GND) level) for a long period of time, the transistors Qp201 is brought into an enhancement state and the transistor Qn201 is brought into a depression state.
In this period A, since a potential of the input terminal of the CMOS inverter 202 (a potential of the output terminal CMOS inverter 201) is in the H-level state (for example, a power supply potential VDD) for a long period of time, the transistors Qp202 is brought into the depression state and the transistor Qn202 is brought into the enhancement state. In this case, when the switch 103 shown in FIG. 10 is turned on and the horizontal transfer clock HCK is supplied to the latch circuit 104, the potential of the input terminal of the CMOS inverter 201 steeply rises in a period B.
In a period C which is as short as a half cycle of the horizontal transfer clock HCK, the potential of the input terminal of the CMOS inverter 201 is brought into the H-level state and the potential of the input terminal of the CMOS inverter 202 is brought into the L-level state. Since time required for changing from an enhancement state to a depression state is longer than time required for changing from the depression state to the enhancement state, all the transistors Qp201, Qn201, Qp202, and Qn202 included in the latch circuit 104 are brought into the enhancement state.
Then, when the horizontal transfer clock HCK falls, since all the transistors Qp201, Qn201, Qp202, and Qn202 are in the enhancement state, the potential of the input terminal of the CMOS inverter 201 (the potential of the output terminal of the CMOS inverter 202) gradually (gently) falls in a period D.